254 lines
8.0 KiB
Diff
254 lines
8.0 KiB
Diff
https://github.com/jcmvbkbc/gcc-xtensa/commit/6b0c9f92fb8e11c6be098febb4f502f6af37cd35.patch
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From 6b0c9f92fb8e11c6be098febb4f502f6af37cd35 Mon Sep 17 00:00:00 2001
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From: Max Filippov <jcmvbkbc@gmail.com>
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Date: Thu, 11 Jun 2015 17:56:57 +0300
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Subject: [PATCH] WIP: xtensa: add -mforce-l32
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Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
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---
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gcc/config/xtensa/constraints.md | 15 ++++++++++++
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gcc/config/xtensa/xtensa.c | 53 +++++++++++++++++++++++++++++++++++++++-
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gcc/config/xtensa/xtensa.md | 49 ++++++++++++++++++++-----------------
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gcc/config/xtensa/xtensa.opt | 4 +++
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4 files changed, 98 insertions(+), 23 deletions(-)
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diff --git a/gcc/config/xtensa/constraints.md b/gcc/config/xtensa/constraints.md
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index 30f4c1f..5fd9337 100644
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--- a/gcc/config/xtensa/constraints.md
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+++ b/gcc/config/xtensa/constraints.md
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@@ -137,3 +137,18 @@
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(and (match_code "reg")
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(match_test "reload_in_progress
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&& REGNO (op) >= FIRST_PSEUDO_REGISTER"))))
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+
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+(define_constraint "Y"
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+ "Memory that is not in a literal pool."
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+ (ior (and (and (match_code "mem")
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+ (match_test "! constantpool_mem_p (op)"))
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+ (match_test "!TARGET_FORCE_L32"))
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+ (and (match_code "reg")
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+ (match_test "reload_in_progress
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+ && REGNO (op) >= FIRST_PSEUDO_REGISTER"))))
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+
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+(define_constraint "Z"
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+ "Memory that is not in a literal pool."
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+ (and (and (match_code "mem")
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+ (match_test "! constantpool_mem_p (op)"))
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+ (match_test "TARGET_FORCE_L32")))
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diff --git a/gcc/config/xtensa/xtensa.c b/gcc/config/xtensa/xtensa.c
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index d8c5b41..559b181 100644
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--- a/gcc/config/xtensa/xtensa.c
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+++ b/gcc/config/xtensa/xtensa.c
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@@ -1824,7 +1824,8 @@ xtensa_legitimate_address_p (machine_mode mode, rtx addr, bool strict)
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return true;
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/* Check for "register + offset" addressing. */
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- if (GET_CODE (addr) == PLUS)
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+ if (GET_CODE (addr) == PLUS &&
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+ (!TARGET_FORCE_L32 || (mode != HImode && mode != QImode)))
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{
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rtx xplus0 = XEXP (addr, 0);
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rtx xplus1 = XEXP (addr, 1);
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@@ -2308,6 +2309,8 @@ printx (FILE *file, signed int val)
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fprintf (file, "0x%x", val);
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}
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+static void
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+output_address_base (FILE *file, rtx addr);
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void
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print_operand (FILE *file, rtx x, int letter)
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@@ -2317,6 +2320,13 @@ print_operand (FILE *file, rtx x, int letter)
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switch (letter)
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{
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+ case 'B':
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+ if (GET_CODE (x) == MEM)
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+ output_address_base (file, XEXP (x, 0));
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+ else
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+ output_operand_lossage ("invalid %%B value");
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+ break;
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+
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case 'D':
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if (GET_CODE (x) == REG || GET_CODE (x) == SUBREG)
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fprintf (file, "%s", reg_names[xt_true_regnum (x) + 1]);
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@@ -2450,6 +2460,47 @@ print_operand (FILE *file, rtx x, int letter)
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}
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}
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+static void
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+output_address_base (FILE *file, rtx addr)
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+{
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+ switch (GET_CODE (addr))
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+ {
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+ default:
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+ fatal_insn ("invalid address", addr);
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+ break;
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+
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+ case REG:
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+ fprintf (file, "%s", reg_names [REGNO (addr)]);
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+ break;
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+
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+ case PLUS:
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+ {
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+ rtx reg = (rtx)0;
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+ rtx offset = (rtx)0;
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+ rtx arg0 = XEXP (addr, 0);
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+ rtx arg1 = XEXP (addr, 1);
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+
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+ if (GET_CODE (arg0) == REG)
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+ {
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+ reg = arg0;
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+ offset = arg1;
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+ }
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+ else if (GET_CODE (arg1) == REG)
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+ {
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+ reg = arg1;
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+ offset = arg0;
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+ }
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+ else
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+ fatal_insn ("no register in address", addr);
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+
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+ if (CONSTANT_P (offset))
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+ fprintf (file, "%s", reg_names [REGNO (reg)]);
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+ else
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+ fatal_insn ("address offset not a constant", addr);
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+ }
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+ break;
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+ }
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+}
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/* A C compound statement to output to stdio stream STREAM the
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assembler syntax for an instruction operand that is a memory
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diff --git a/gcc/config/xtensa/xtensa.md b/gcc/config/xtensa/xtensa.md
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index a577aa3..f56c45e 100644
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--- a/gcc/config/xtensa/xtensa.md
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+++ b/gcc/config/xtensa/xtensa.md
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@@ -532,26 +532,28 @@
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;; Zero-extend instructions.
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(define_insn "zero_extendhisi2"
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- [(set (match_operand:SI 0 "register_operand" "=a,a")
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- (zero_extend:SI (match_operand:HI 1 "nonimmed_operand" "r,U")))]
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+ [(set (match_operand:SI 0 "register_operand" "=a,a,a")
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+ (zero_extend:SI (match_operand:HI 1 "nonimmed_operand" "r,Y,Z")))]
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""
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"@
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extui\t%0, %1, 0, 16
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- l16ui\t%0, %1"
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- [(set_attr "type" "arith,load")
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+ l16ui\t%0, %1
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+ ssa8l\t%B1 ; srli\t%0, %B1, 2 ; slli\t%0, %0, 2 ; l32i\t%0, %0, 0 ; srl\t%0, %0 ; extui\t%0, %0, 0, 16"
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+ [(set_attr "type" "arith,load,load")
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(set_attr "mode" "SI")
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- (set_attr "length" "3,3")])
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+ (set_attr "length" "3,3,18")])
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(define_insn "zero_extendqisi2"
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- [(set (match_operand:SI 0 "register_operand" "=a,a")
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- (zero_extend:SI (match_operand:QI 1 "nonimmed_operand" "r,U")))]
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+ [(set (match_operand:SI 0 "register_operand" "=a,a,a")
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+ (zero_extend:SI (match_operand:QI 1 "nonimmed_operand" "r,Y,Z")))]
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""
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"@
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extui\t%0, %1, 0, 8
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- l8ui\t%0, %1"
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- [(set_attr "type" "arith,load")
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+ l8ui\t%0, %1
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+ ssa8l\t%B1 ; srli\t%0, %B1, 2 ; slli\t%0, %0, 2 ; l32i\t%0, %0, 0 ; srl\t%0, %0 ; extui\t%0, %0, 0, 8"
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+ [(set_attr "type" "arith,load,load")
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(set_attr "mode" "SI")
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- (set_attr "length" "3,3")])
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+ (set_attr "length" "3,3,18")])
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;; Sign-extend instructions.
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@@ -569,15 +571,16 @@
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})
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(define_insn "extendhisi2_internal"
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- [(set (match_operand:SI 0 "register_operand" "=B,a")
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- (sign_extend:SI (match_operand:HI 1 "sext_operand" "r,U")))]
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+ [(set (match_operand:SI 0 "register_operand" "=B,a,a")
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+ (sign_extend:SI (match_operand:HI 1 "sext_operand" "r,r,Y")))]
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""
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"@
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sext\t%0, %1, 15
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+ slli\t%0, %1, 16 ; srai\t%0, %0, 16
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l16si\t%0, %1"
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- [(set_attr "type" "arith,load")
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+ [(set_attr "type" "arith,arith,load")
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(set_attr "mode" "SI")
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- (set_attr "length" "3,3")])
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+ (set_attr "length" "3,6,3")])
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(define_expand "extendqisi2"
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[(set (match_operand:SI 0 "register_operand" "")
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@@ -796,8 +799,8 @@
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})
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(define_insn "movhi_internal"
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- [(set (match_operand:HI 0 "nonimmed_operand" "=D,D,a,a,a,U,*a,*A")
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- (match_operand:HI 1 "move_operand" "M,d,r,I,U,r,*A,*r"))]
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+ [(set (match_operand:HI 0 "nonimmed_operand" "=D,D,a,a,a,a,U,*a,*A")
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+ (match_operand:HI 1 "move_operand" "M,d,r,I,Y,Z,r,*A,*r"))]
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"xtensa_valid_move (HImode, operands)"
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"@
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movi.n\t%0, %x1
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@@ -805,12 +808,13 @@
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mov\t%0, %1
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movi\t%0, %x1
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%v1l16ui\t%0, %1
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+ ssa8l\t%B1 ; srli\t%0, %B1, 2 ; slli\t%0, %0, 2 ; %v1l32i\t%0, %0, 0 ; srl\t%0, %0 ; extui\t%0, %0, 0, 16
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%v0s16i\t%1, %0
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rsr\t%0, ACCLO
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wsr\t%1, ACCLO"
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- [(set_attr "type" "move,move,move,move,load,store,rsr,wsr")
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+ [(set_attr "type" "move,move,move,move,load,load,store,rsr,wsr")
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(set_attr "mode" "HI")
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- (set_attr "length" "2,2,3,3,3,3,3,3")])
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+ (set_attr "length" "2,2,3,3,3,18,3,3,3")])
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;; 8-bit Integer moves
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@@ -824,8 +828,8 @@
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})
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(define_insn "movqi_internal"
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- [(set (match_operand:QI 0 "nonimmed_operand" "=D,D,a,a,a,U,*a,*A")
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- (match_operand:QI 1 "move_operand" "M,d,r,I,U,r,*A,*r"))]
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+ [(set (match_operand:QI 0 "nonimmed_operand" "=D,D,a,a,a,a,U,*a,*A")
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+ (match_operand:QI 1 "move_operand" "M,d,r,I,Y,Z,r,*A,*r"))]
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"xtensa_valid_move (QImode, operands)"
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"@
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movi.n\t%0, %x1
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@@ -833,12 +837,13 @@
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mov\t%0, %1
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movi\t%0, %x1
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%v1l8ui\t%0, %1
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+ ssa8l\t%B1 ; srli\t%0, %B1, 2 ; slli\t%0, %0, 2 ; %v1l32i\t%0, %0, 0 ; srl\t%0, %0 ; extui\t%0, %0, 0, 8
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%v0s8i\t%1, %0
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rsr\t%0, ACCLO
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wsr\t%1, ACCLO"
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- [(set_attr "type" "move,move,move,move,load,store,rsr,wsr")
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+ [(set_attr "type" "move,move,move,move,load,load,store,rsr,wsr")
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(set_attr "mode" "QI")
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- (set_attr "length" "2,2,3,3,3,3,3,3")])
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+ (set_attr "length" "2,2,3,3,3,18,3,3,3")])
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;; Sub-word reloads from the constant pool.
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diff --git a/gcc/config/xtensa/xtensa.opt b/gcc/config/xtensa/xtensa.opt
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index 2fd6cee..02020d2 100644
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--- a/gcc/config/xtensa/xtensa.opt
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+++ b/gcc/config/xtensa/xtensa.opt
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@@ -41,3 +41,7 @@ Intersperse literal pools with code in the text section
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mserialize-volatile
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Target Report Mask(SERIALIZE_VOLATILE)
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-mno-serialize-volatile Do not serialize volatile memory references with MEMW instructions
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+
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+mforce-l32
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+Target Report Mask(FORCE_L32)
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+Use l32i to access 1- and 2-byte quantities in memory instead of l8ui/l16ui
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